關鍵字查詢 | 類別:會議論文 | | 關鍵字:A 1.2 V 500 MHz 32-bit carry-lookahead adder

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序號 學年期 教師動態
1 90/1 電機系 鄭國興 副教授 會議論文 發佈 A 1.2 V 500 MHz 32-bit carry-lookahead adder , [90-1] :A 1.2 V 500 MHz 32-bit carry-lookahead adder會議論文A 1.2 V 500 MHz 32-bit carry-lookahead adder鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong淡江大學電機工程學系Institute of Electrical and Electronics Engineers (IEEE)Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on (Volume:2 ), pp.765-768In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 μm 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.tku_id:000094759;Made available in DSpace on 2010-04-
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