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序號 學年期 教師動態
1 87/2 電機系 楊維斌 副教授 期刊論文 發佈 The charge-transfer feedback-controlled split-path CMOS buffer , [87-2] :The charge-transfer feedback-controlled split-path CMOS buffer期刊論文The charge-transfer feedback-controlled split-path CMOS bufferCheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi淡江大學電機工程學系New York: Institute of Electrical and Electronics Engineers (IEEE)IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46(3), pp.346-348Abstract—A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the shortcircuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper
2 87/2 電機系 鄭國興 副教授 期刊論文 發佈 The charge-transfer feedback-controlled split-path CMOS buffer , [87-2] :The charge-transfer feedback-controlled split-path CMOS buffer期刊論文The charge-transfer feedback-controlled split-path CMOS bufferCheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi淡江大學電機工程學系New York: Institute of Electrical and Electronics Engineers (IEEE)IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46(3), pp.346-348Abstract—A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the shortcircuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper
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