關鍵字查詢 | 類別:期刊論文 | | 關鍵字:A Novel Architecture for High-Speed Viterbi Decoder

[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 03 筆查詢結果
序號 學年期 教師動態
1 95/1 電機系 李維聰 教授 期刊論文 發佈 A Novel Architecture for High-Speed Viterbi Decoder , [95-1] :A Novel Architecture for High-Speed Viterbi Decoder期刊論文A Novel Architecture for High-Speed Viterbi Decoder李揚漢; Lee, Yang-han; 詹益光; Jan, Yih-guang; Tseng, Hsien-wei; Chuang, Ming-hsueh; Peng, Chiung-hsuan; 李維聰; Lee, Wei-tsong; Chen, Chih-tsung淡江大學電機工程學系Viterbi Decoder;Add-Compare-Select Unit ACSU;Cyclic-Shift Register Unit CSRU;Pseudo-Correlator Unit PCU淡江大學淡江理工學刊=Tamkang journal of science and engineering 9(4), pp.343-352In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not on
2 95/1 電機系 李揚漢 教授 期刊論文 發佈 A Novel Architecture for High-Speed Viterbi Decoder , [95-1] :A Novel Architecture for High-Speed Viterbi Decoder期刊論文A Novel Architecture for High-Speed Viterbi Decoder李揚漢; Lee, Yang-han; 詹益光; Jan, Yih-guang; Tseng, Hsien-wei; Chuang, Ming-hsueh; Peng, Chiung-hsuan; 李維聰; Lee, Wei-tsong; Chen, Chih-tsung淡江大學電機工程學系Viterbi Decoder;Add-Compare-Select Unit ACSU;Cyclic-Shift Register Unit CSRU;Pseudo-Correlator Unit PCU淡江大學淡江理工學刊=Tamkang journal of science and engineering 9(4), pp.343-352In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not on
3 95/1 電機系 詹益光 教授 期刊論文 發佈 A Novel Architecture for High-Speed Viterbi Decoder , [95-1] :A Novel Architecture for High-Speed Viterbi Decoder期刊論文A Novel Architecture for High-Speed Viterbi Decoder李揚漢; Lee, Yang-han; 詹益光; Jan, Yih-guang; Tseng, Hsien-wei; Chuang, Ming-hsueh; Peng, Chiung-hsuan; 李維聰; Lee, Wei-tsong; Chen, Chih-tsung淡江大學電機工程學系Viterbi Decoder;Add-Compare-Select Unit ACSU;Cyclic-Shift Register Unit CSRU;Pseudo-Correlator Unit PCU淡江大學淡江理工學刊=Tamkang journal of science and engineering 9(4), pp.343-352In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not on
[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 03 筆查詢結果