會議論文
| 學年 | 91 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2002-08-06 |
| 作品名稱 | The CMOS on-chip oscillator based on level tracking technique |
| 作品名稱（其他語言） | |
| 著者 | Chang, Chia-yang; Chen, Po-chang; Yang, Ching-yang; 李揚漢; Lee, Yang-han |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on |
| 會議地點 | Taipei, Taiwan |
| 摘要 | In this paper, we propose the architecture of a CMOS fully integrated level-locked loop (LLL). A 455 kHz LLL without external reference signal achieves the target of 1 percent variation, and consumes 9 mW with 3.6 V power supply in a standard 0.5 μm CMOS process. The frequency-to-voltage converter (FVC) in the LLL, built upon the charge redistribution principle, can decrease the process variation. A programmable controller is developed to increase the frequency accuracy. The voltage-controlled oscillator (VCO) is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. According to the main circuits, operated at 1.8 V provided by a regulator, the output frequency is accurately for 455 kHz from 2.0 V to 3.6 V. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20020806~20020808 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 出處 | ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on, pp.197-200 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38600 ) |