會議論文
| 學年 | 86 |
|---|---|
| 學期 | 2 |
| 發表日期 | 1998-05-31 |
| 作品名稱 | A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on |
| 會議地點 | |
| 摘要 | In this paper, we aim to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6 μm SPDM CMOS process. The simulation shows that this chip can operate in the range between 60 MHz and 400 MHz, and operates at 4× the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1 ns. The IC consists of 4026 MOS transistors and the core size of the chip layout is 923 μm×921 μm. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 19980531~19980603 |
| 通訊作者 | |
| 國別 | Monterey, CA, USA USA |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 出處 | Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:3 ), pp.554-557 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38553 ) |