期刊論文
| 學年 | 87 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 1999-07-01 |
| 作品名稱 | The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | New York: Institute of Electrical and Electronics Engineers (IEEE) |
| 著錄名稱、卷期、頁數 | IEEE Transactions on Circuits and Systems Part 2: Analog and Digital Signal Processing 46(7), pp.945-950 |
| 摘要 | The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture. In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC’s 0.6-m SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 1057-7130 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | 電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/46248 ) |