會議論文
學年 | 86 |
---|---|
學期 | 1 |
發表日期 | 1997-08-21 |
作品名稱 | The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop |
作品名稱(其他語言) | |
著者 | Chen, Kuang-Yuan; Chiang, Jen-Shiun |
作品所屬單位 | 淡江大學電機工程學系 |
出版者 | |
會議名稱 | 第八屆超大型積體電路設計暨計算機輔助設計技術研討會=The 8th VLSI Design/CAD Symposium |
會議地點 | 南投縣, 臺灣 |
摘要 | This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6um SPDM CMOS process. The simulation shows that this chip can operate in the range between 60MHz and 400MHz, and operates at 4x the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1ns. The chip consists of 4026 MOS transistors and the core size of the VLSI layout is 923.mu.m*921.mu.m. |
關鍵字 | 全數位;鎖相迴路;電路設計;數位控制振盪器;頻率比較器;相位偵測器;All Digital;Phase Locked Loop;Circuit Design;Digital Control Oscillator;Frequency Comparator;Phase Detector |
語言 | en |
收錄於 | |
會議性質 | 國內 |
校內研討會地點 | |
研討會時間 | 19970821~19970823 |
通訊作者 | |
國別 | TWN |
公開徵稿 | Y |
出版型式 | 紙本 |
出處 | 第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium,頁173-176 |
相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96023 ) |