會議論文
| 學年 | 92 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2003-08-12 |
| 作品名稱 | 2.4GHz CMOS Power Amplifier with Dynamic Bias Circuits for Efficiency Improvement |
| 作品名稱（其他語言） | |
| 著者 | Chiang, Jen-Shiun; Chen, Jim-Wen |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium |
| 會議地點 | 花蓮縣, 臺灣 |
| 摘要 | This work presents a dynamic gate bias circuit for bias control to maximize power added efficiency based on the class-A two-stage power amplifier. The proposed circuits are composed of two NMOS transistors, a capacitor for coupling RF input signal, four resistors for bias, and a RF choke. The circuit is implemented due to the bias control at the two-stage power amplifier to improve the overall power added efficiency and delivers 23dBm output power at 2.4GHz. The circuit can improve the power efficiency for small RF signals. The simulation indicates that the efficiency is improved more than 100% at 0dBm input signal. This proposed power amplifier can be applied to the transceivers of IEEE 802.11a, 11b, and Bluetooth. |
| 關鍵字 | 2.4十億赫茲;功率放大器;動態偏壓電路;效率改善;偏壓控制;2.4 GHz;Power amplifier;Dynamic bias circuit;Effeciencyimprovement;Bias control |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 20030812~20030815 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁125-128 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96036 ) |