會議論文
| 學年 | 90 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2001-09-26 |
| 作品名稱 | An Overlapped Row Column High Throughput DCT/IDCT Architecture for Real-Time Image and Video System |
| 作品名稱（其他語言） | |
| 著者 | Chiang, Jen-Shiun; Chiu, Yi-Fang |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 二ＯＯ一年第七屆分散式多媒體系統國際研討會=The Seventh International Conference on Distributed Multimedia System |
| 會議地點 | 臺北縣, 臺灣 |
| 摘要 | The discrete cosine transform (DCT) has been widely used as the coreof digital image and video signal compression. In this paper, wepresent a high throughput 8x8 2D DCT/IDCT architecture which is wellsuited for the application in real time image or video system. Insteadof the transport RAM in traditional architecture, the overlappedrow-column operation is used that can reduce the total latency of thepipelined structure. There are several characteristics of this DCT:(1) the multiplication is accomplished by using look-up table andpartial sum adder to reduce the area and cycle time. (2) With a highthroughput rate pipelined architecture and (3) row-column overlappedtechnique is used for this DCT/IDCT. It possesses no matrixtransposition and is suitable for VLSI implementation. We havedesigned a DCT/IDCT chip using the architecture by Compass standardcell library under TSMC 0.35um 1P4M process. The chip occupies4278.4umx4278.4um and consists of 119,181 transistors. Simulationresults show the proposed architecture can work well with 100MHz thatmeets the requirement of many real-time digital video systems. |
| 關鍵字 | 離散餘弦轉換;即時;影像系統;視訊系統;重疊式行列運算;Discrete Cosine Transform;Real Time;Image System;Video System;Overlapped Row Column Operation |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | 淡水校園 |
| 研討會時間 | 20010926~20010928 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 第七屆國際分散式多媒體系統會議論文集，頁273-276 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95977 ) |