期刊論文
| 學年 | 93 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 2005-07-01 |
| 作品名稱 | Design of an Adjustable-way Cache for Energy Reduction |
| 作品名稱（其他語言） | |
| 著者 | Chen, Hsin-chuan; Chiang, Jen-shiun |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Taipei : Chinese Institute of Chemical Engineers |
| 著錄名稱、卷期、頁數 | Journal of the Chinese Institute of Engineers=中國工程學刊 28(4), pp. 691- 700 |
| 摘要 | Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an n‐way set‐associative cache configures the cache with lower associativity (less than n) due to only enabling fewer subarrays of the tag memory and data memory. However, the performance is still maintained at the same level as in a conventional set‐associative cache or direct‐mapped cache. Adjustable‐way set‐associative caches can also be applied to multiprocessor systems to reduce the average, overall system, energy dissipation. |
| 關鍵字 | Associativity;Adjustable-way;Average energy dissipation;Multiprocessor systems |
| 語言 | en |
| ISSN | 0253-3839 |
| 期刊性質 | 國內 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60874 ) |