會議論文
| 學年 | 93 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2005-04-28 |
| 作品名稱 | An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme |
| 作品名稱（其他語言） | |
| 著者 | Chiang, Jen-Shiun; Hsia, Chih-Hsien |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | New York: Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | 2005年國際系統與信號研討會 2005=International Conference on System & Signals (ICSS2005) |
| 會議地點 | 高雄, 臺灣 |
| 摘要 | In this paper, we propose a highly efficient VLSI architecture for 2-D lifting-based 5/3 filter discrete wavelet transform (DWT). The architecture is based on the pipelined and folding scheme processing to achieve near 100% hardware utilization ratio and reduce the silicon area. The advantages of the proposed DWT have the characteristics of higher hardware utilization, less memory requirement, and regular data flow. It is suitable for VLSI implementation and can be applied to real-time operating of JPEG2000 and MPEG4 applications. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20050428~20050429 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | 2005年國際系統與信號研討會論文集=Proceedings of 2005 International Conference on System & Signals (ICSS2005), 4p. |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70311 ) |