會議論文
| 學年 | 93 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2005-05-23 |
| 作品名稱 | VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications |
| 作品名稱（其他語言） | |
| 著者 | Chiang, Jen-Shiun; Hsia, Chih-Hsien; Chen, Hsin-Jung; Lo, Te-Jung |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | New York: Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on |
| 會議地點 | |
| 摘要 | The paper presents a low memory and high speed VLSI architecture for 2D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operation of JPEG2000 and MPEG-4 applications. Basing on the proposed architecture, we designed and simulated a 2D DWT VLSI chip by 0.35 弮m 1P4M CMOS technology. The memory requirement of the N?N 2D DWT is N, and it can operate at 100 MHz clock frequency. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20050523~20050526 |
| 通訊作者 | |
| 國別 | |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on Vol. 5, pp.4554-4557 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70594 ) |