會議論文
| 學年 | 97 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2009-05-24 |
| 作品名稱 | Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000 |
| 作品名稱（其他語言） | |
| 著者 | Li, Wei-ming; Hsia, Chih-Hsien; Chiang, Jen-Shiun |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | New York: Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on |
| 會議地點 | |
| 摘要 | In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2D DWT) for motion-JPEG2000. The proposed 2D DWT architecture consists of a 1D row processor, internal memory, and a 1D column processor. The main advantage of this 2D DWT is to reduce the internal memory requirement significantly. For an NtimesN image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | |
| 校內研討會地點 | |
| 研討會時間 | 20090524~20090527 |
| 通訊作者 | |
| 國別 | |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp.750-753 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80831 ) |