會議論文
| 學年 | 93 |
|---|---|
| 學期 | 2 |
| 發表日期 | 2005-03-28 |
| 作品名稱 | Low-power way-predicting cache using valid-bit pre-decision for parallel architectures |
| 作品名稱（其他語言） | |
| 著者 | Chen, Hsin-Chuan; Chiang, Jen-Shiun |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Los Alamitos, California：Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on |
| 會議地點 | 臺北縣, 臺灣 |
| 摘要 | Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By validbit pre-decision, it significantly helps in improving the average energy saving of the conventional waypredicting cache without valid-bit pre-decision, especially for with large associativity and small subblock size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | 淡水校園 |
| 研討會時間 | 20050328~20050330 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on, vol.2, pp.203-206 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70475 ) |