會議論文
| 學年 | 96 |
|---|---|
| 學期 | 2 |
| 發表日期 | 2008-06-23 |
| 作品名稱 | Low cost architecture for JPEG2000 encoder without code-block memory |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Lin, Tsung-ta; Hwang, Ting-hao |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | IEEE |
| 會議名稱 | Multimedia and Expo, 2008 IEEE International Conference on |
| 會議地點 | Hannover, Germany |
| 摘要 | The amount of memory required for code-block is one of the most important issues in JPEG2000 encoder chip implementation. This work tries to unify the output scanning order of the 2D-DWT and the processing order of the EBCOT and further to eliminate the code-block memory completely eliminated. We also propose a new architecture for embedded block coding (EBC), code-block switch adaptive embedded block coding (CS-AEBC), which can skip the insignificant bit-planes to reduce the computation time and save power consumption. Besides, a new dynamic rate distortion optimization (RDO) approach is proposed to reduce the computation time when the EBC processes lossy compression operation. The total memory required for the proposed JPEG2000 is only 2KB of internal memory, and the bandwidth required for the external memory is 2.1 B/cycle. |
| 關鍵字 | 2D-DWT;EBCOT;JPEG2000;RDO |
| 語言 | |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20080623-20080626 |
| 通訊作者 | |
| 國別 | DEU |
| 公開徵稿 | Y |
| 出版型式 | |
| 出處 | Multimedia and Expo, 2008 IEEE International Conference on, pp.137-140 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70471 ) |