期刊論文

標題 A low-jitter phase-interpolation DDS using dual-slope integration
學年 93
學期 1
出版(發表)日期 2004/09/25
作品名稱 A low-jitter phase-interpolation DDS using dual-slope integration
作品名稱(其他語言)
著者 Chen, Hsin-chuan; 江正雄; Chiang, Jen-shiun
單位 淡江大學電機工程學系
出版者
著錄名稱、卷期、頁數 IEICE Electronics Express 1(12), pp.333-338
摘要 In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.
關鍵字 phase-interpolation DDS;dual-slope integration;capacitance error;delay time error
語言 英文(美國)
ISSN 1349-2543
期刊性質 國外
收錄於
產學合作
通訊作者
審稿制度
國別 日本
公開徵稿
出版型式 ,電子版