期刊論文
| 學年 | 91 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2003-01-01 |
| 作品名稱 | A Radix-4 New Svota-Tung Divider with Constant Timing Complexity for Precsaling |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Chiang, Jen-shiun; Tsai, Min-show |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 著錄名稱、卷期、頁數 | Kluwer Journal of VLSI Signal Processing 33(1/2), pp.117-124 |
| 摘要 | A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers. |
| 關鍵字 | computer arithmetic;floating-point division;new Svoboda-Tung;division;prescaling;radix-4;signed digit number system;Svoboda-Tung division |
| 語言 | en_US |
| ISSN | 0922-5773 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60812 ) |