期刊論文
| 學年 | 91 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2002-12-01 |
| 作品名稱 | Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm |
| 作品名稱（其他語言） | |
| 著者 | Kuo, Chien-hung; Hsueh, Tzu-chien; Liu, Shen-iuan |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | New York: Springer New York LLC |
| 著錄名稱、卷期、頁數 | Analog Integrated Circuits and Signal Processing 33(3), pp.289-300 |
| 摘要 | A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is −7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 0925-1030 1573-1979 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60809 ) |