期刊論文
| 學年 | 96 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 2008-03-01 |
| 作品名稱 | Faulty-Tolerant Algorithm for Mapping a Complete Binary Tree in an IEH |
| 作品名稱（其他語言） | |
| 著者 | Wu, Shih-Jung; Jen-Chih Lin; Huan-Chao Keh |
| 單位 | 淡江大學資訊創新與科技學系 |
| 出版者 | Zographou: World Scientific and Engineering Academy and Society |
| 著錄名稱、卷期、頁數 | WSEAS Transactions on Computers 7(3), p.83-88 |
| 摘要 | Different parallel architectures may require different algorithms to make the existent algorithms on one architecture be easily transformed to or implemented on another architecture. This paper proposes a novel algorithm for embedding complete binary trees in a faulty Incrementally Extensible Hypercube (IEH). Furthermore, to obtain the replaceable node of the faulty node, 2-expansion is permitted such that up to (n+1) faults can be tolerated with dilation 3, congestion 1 and load 1. The presented embedding methods are optimized mainly for balancing the processor loads, while minimizing dilation and congestion as far as possible. According to the result, we can map the parallel algorithms developed by the structure of complete binary tree in an IEH. These methods of reconfiguring enable extremely high-speed parallel computation. |
| 關鍵字 | Hypercube;Incrementally Extensible Hypercube;Complete binary tree;Fault-Tolerance;Embedding |
| 語言 | en |
| ISSN | 1109-2750; 2224-2872 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | GRC |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/64012 ) |