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教師資料查詢 | 教師：饒建奇

# 學年期 類別 標題
301 100-2 教學計畫表 電機系電資三：硬體描述語言 TETAB3E2357 0A
302 100-2 教學計畫表 電機系電機三：微處理機實驗 TETCB3E1565 0B
303 101-1 教學計畫表 電機系電資三：作業系統 TETAB3E0175 0A
304 100-2 教學計畫表 電機系電資一：資訊概論 TETAB1E1034 2R
305 100-1 研究獎勵 Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
306 100-1 研究獎勵 Power-Aware Multi-Chains Encoding Scheme for System-on-a-chip in Low-Cost Environment
307 100-1 研究獎勵 An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
308 101-1 論文指導 電機一電路組 林承瀚
309 101-1 論文指導 電機一機器人 陳昱璇
310 101-1 論文指導 電機一碩專班 陳威豪
311 100-1 研究報告 低捕捉功率快速掃描測試架構之研究
312 94-1 會議論文 智慧型無線光導盲杖導引系統暨導盲機器人之設計
313 97-1 會議論文 An Efficient Scheduling Algorithm for Testing SOC with Multi-Frequency TAM
314 98-1 會議論文 A Novel Gated Scan-Cell Scheme for Low Capture Power (LCP) in At-Speed Testing
315 92-1 會議論文 A Datapath-Based Debugging Mechanism for RTL Description
316 96-2 會議論文 A New Double-edge Triggered Design with Low-power consumption and High-speed
317 98-1 會議論文 A New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
318 95-2 會議論文 A New Algorithm for Latch-Up Check Based on Look-Up Table
319 98-2 會議論文 Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
320 95-1 會議論文 Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
321 99-1 會議論文 An Filling Methodology for Efficient Compaction of Test Responses with Unknowns
322 97-2 會議論文 Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression
323 98-2 會議論文 Multi-Chains Encoding Scheme in Low-Cost ATE
324 97-2 會議論文 A Novel Constructive Data Compression Scheme for Shifting-in Power Reduction with Multiple Scan-chains Design
325 97-2 會議論文 A Novel Clock Gating Scheme of Scan Chains for Capture Power Reduction
326 96-1 會議論文 A Novel High-Speed SOC Test Scheme Using Virtual TAMs
327 96-2 會議論文 An Efficient Test-Data Compaction for Low Power VLSI Testing
328 97-1 會議論文 Test Slice Difference Technique for Low Power Testing
329 97-1 會議論文 The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design
330 99-2 期刊論文 Power-aware compression scheme for multiple scan-chain