關鍵字查詢 | 類別:會議論文 | | 關鍵字:Reconfigurable multiple scan-chains for reducing test application time of SOCs

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序號 學年期 教師動態
1 93/2 電機系 饒建奇 副教授 會議論文 發佈 Reconfigurable multiple scan-chains for reducing test application time of SOCs , [93-2] :Reconfigurable multiple scan-chains for reducing test application time of SOCs會議論文Reconfigurable multiple scan-chains for reducing test application time of SOCsRau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing淡江大學電機工程學系N.Y.: Institute of Electrical and Electronic Engineers (IEEE)Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:6 ), pp.5846-5849We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.2015-08-04 補正完成 by 宏孟;tku_id: 000116686;Made available in DSp
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