關鍵字查詢 | 類別:會議論文 | | 關鍵字:Multiprocessor architecture reconciling symbolic with numerical processing

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序號 學年期 教師動態
1 77/2 資管系 李鴻璋 副教授 會議論文 發佈 Multiprocessor architecture reconciling symbolic with numerical processing , [77-2] :Multiprocessor architecture reconciling symbolic with numerical processing會議論文Multiprocessor architecture reconciling symbolic with numerical processingJang, G. S. ; Lai, F. ; 李鴻璋; Lee, H. C. ; Maa, Y. C. ; Parng, T. M. ; Tsai, J. Y.淡江大學資訊管理學系IEEEInternational symposium on VLSI technology, system and applications, pp.365-370The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type check
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