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序號 學年期 教師動態
1 101/1 機器人中心 翁慶昌 教授 會議論文 發佈 Hardware accelerator design for image processing , [101-1] :Hardware accelerator design for image processing會議論文Hardware accelerator design for image processingLi, S.A.; Wong, C.C.; Yang, C.Y.; Chen, L.F.FPGA;human-machine interface;hardware acceleratorLecture Notes in Computer Science 7429, pp.436-437This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.en國際無20120820~20120823Shih-An Li是GBRJoint Proceedings of the 13th
2 101/1 電機系 李世安 副教授 會議論文 發佈 Hardware Accelerator Design for Image Processing , [101-1] :Hardware Accelerator Design for Image Processing會議論文Hardware Accelerator Design for Image ProcessingLi, S.A.; Wong, C.C.; Yang, C.Y.; Chen, L.F.淡江大學電機工程學系FPGA; human-machine interface; hardware acceleratorBerlin: Springer Berlin HeidelbergLecture Notes in Computer Science 7429, pp.436-437This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.tku_id: 000126769@@d
3 97/2 電機系 李世安 副教授 會議論文 發佈 Hardware accelerator design for image process , [97-2] :Hardware accelerator design for image process會議論文Hardware accelerator design for image process李世安淡江大學電機工程學系2009 National Symposium on System Science and Engineering (NSSSE’09), Tamsumi, Taipei Hsien, R.O.C.tku_id: 000126769;Submitted by 曉芬 游 (139570@mail.tku.edu.tw) on 2011-10-23T13:17:27Z No. of bitstreams: 0;Made available in DSpace on 2011-10-23T13:17:28Z (GMT). No. of bitstreams: 0國內<links><record><name>機構典藏連結</name><url>http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70429</url></record></links>
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