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1 88/2 電機系 饒建奇 副教授 會議論文 發佈 A timing-driven pseudo-exhaustive testing of VLSI circuits , [88-2] :A timing-driven pseudo-exhaustive testing of VLSI circuits會議論文A timing-driven pseudo-exhaustive testing of VLSI circuitsChang, S. C.; Rau, J. C.淡江大學電機工程學系Institute of Electrical and Electronics Engineers (IEEE)Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.665-668The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.2015-07-27 補正完成 by 宏孟;tku_id
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