關鍵字查詢 | 類別:會議論文 | | 關鍵字:A novel reseeding mechanism for pseudo-random testing of VLSI circuits

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序號 學年期 教師動態
1 93/2 電機系 饒建奇 副教授 會議論文 發佈 A novel reseeding mechanism for pseudo-random testing of VLSI circuits , [93-2] :A novel reseeding mechanism for pseudo-random testing of VLSI circuits會議論文A novel reseeding mechanism for pseudo-random testing of VLSI circuitsRau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han淡江大學電機工程學系Institute of Electrical and Electronics Engineers (IEEE)Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:3 ), pp.2979-2982During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random, and use an additional bit counter to improve test length and achieve high fault coverage. The fact is that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change them to useful
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