關鍵字查詢 | 類別:會議論文 | | 關鍵字:A Datapath-Based Debugging Mechanism for RTL Description

[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 02 筆查詢結果
序號 學年期 教師動態
1 92/1 電機系 饒建奇 副教授 會議論文 發佈 A Datapath-Based Debugging Mechanism for RTL Description , [92-1] :A Datapath-Based Debugging Mechanism for RTL Description會議論文A Datapath-Based Debugging Mechanism for RTL DescriptionRau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao淡江大學電機工程學系資料路徑;暫存器轉移層次;雜道層次;硬體描述語言;錯誤空間;Data-path;Register-transfer level (RTL);Gate level;Hardwaredescription language (HDL);Error space第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁153-156中興大學電機系; 中興大學資科系; 孟堯晶片中心In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.20140213add by 陸桂英;tku_id: 000116686;Submitted by 桂英 陸 (deer@mail.tku.edu.tw) on 2014-02-13T03:37:3
2 92/1 電機系 饒建奇 副教授 會議論文 發佈 A Datapath-Based Debugging Mechanism for RTL Description , [92-1] :A Datapath-Based Debugging Mechanism for RTL Description會議論文A Datapath-Based Debugging Mechanism for RTL Description饒建奇淡江大學電機工程學系花蓮The 14th VLSI Design/CAD Symposium.2003.,tku_id: 000116686;Submitted by 曉芬 游 (139570@mail.tku.edu.tw) on 2011-10-23T13:04:35Z No. of bitstreams: 0;Made available in DSpace on 2011-10-23T13:04:36Z (GMT). No. of bitstreams: 0國內<links><record><name>機構典藏連結</name><url>http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70227</url></record></links>
[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 02 筆查詢結果