關鍵字查詢 | 類別:會議論文 | | 關鍵字:A Core-Based Test Methodology for Fast Multipliers

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序號 學年期 教師動態
1 92/1 電機系 饒建奇 副教授 會議論文 發佈 A Core-Based Test Methodology for Fast Multipliers , [92-1] :A Core-Based Test Methodology for Fast Multipliers會議論文A Core-Based Test Methodology for Fast MultipliersRau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu淡江大學電機工程學系快速多工器;測試策略;核心基礎;矽智產;系統單晶片;數位信號處理器;Fast multiplexer;Test strategy;Core-based;Intellectuall property(IP);System-on-a-chip (SOC);Digital signal processor (DSP)第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁437-440中興大學電機系; 中興大學資科系; 孟堯晶片中心To test core-based SoCs, an important step is to get the efficient test vectors for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test vectors at higher level than at logic level. For core vendors, they design their IP cores not only add design for testability (DFT) strategyf or its cores, but also provide the most effective test vectors for core users. Based on this issue, in this paper, we propose a method to generate pseudo-exhaustive test patterns at functiona
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