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序號 學年期 教師動態
1 90/1 電機系 鄭國興 副教授 會議論文 發佈 A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency , [90-1] :A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency會議論文A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency鄭國興; Cheng, Kuo-hsing; Chen, Yu-jung淡江大學電機工程學系Institute of Electrical and Electronics Engineers (IEEE)ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, pp.139-143In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC's 0-35 μ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cyc
2 92/1 電機系 鄭國興 副教授 會議論文 發佈 A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming , [92-1] :A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming會議論文A 14-Bit, 200 MS/S Digital-To-Analog Converter Without TrimmingCheng, Kuo-Hsing; Li, Po-Yu; Chen, Tsung-Shen淡江大學電機工程學系數位類比轉換器;修剪;差動非線性誤差;累增非線性誤差;最小位元;Digital analog converter (DAC);Trimming;Differential non-linearity(DNL);Integral non-linearity (INL);Least significant bit (LSB)第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁205-208中興大學電機系; 中興大學資科系; 孟堯晶片中心In this paper, a 14-bit, low DNL error, 200M sample/s, current-steering digital to analog converter without trimming is proposed and analyzed. A novel feedback gain stage current mirror is proposed for improving the DAC's differential non-linearity (DNL) and integral nonlinearity(INL) characteristic. The proposed current steering DAC is designed and an experimental chip was implemented based on the TSMC 0.25um 1P5M CMOS process with a 2.5V supply voltage The post-layout simulation results show that both the DNL and INL oft his DAC are g
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