關鍵字查詢 | 類別:期刊論文 | | 關鍵字:High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 01 筆查詢結果
序號 學年期 教師動態
1 97/2 電機系 楊維斌 副教授 期刊論文 發佈 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer , [97-2] :High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer期刊論文High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency SynthesizerLo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing淡江大學電機工程學系dynamic D flip-flops; counters; prescalers; ultra-low-voltage designTokyo: Denshi Jouhou Tsuushin GakkaiIEICE Transactions on Electronics E92-C(6), pp.890-893A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay p
[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 01 筆查詢結果