關鍵字查詢 | 類別:期刊論文 | | 關鍵字:Hardware/software co-design for particle swarm optimization algorithm

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序號 學年期 教師動態
1 100/1 電機系 李世安 副教授 期刊論文 發佈 Hardware/software co-design for particle swarm optimization algorithm , [100-1] :Hardware/software co-design for particle swarm optimization algorithm期刊論文Hardware/software co-design for particle swarm optimization algorithmLi, Shih-An; Hsu, Chen-Chien; Wong, Ching-Chang; Yu, Chia-Jun淡江大學電機工程學系HW/SW co-design; Particle swarm optimization (PSO); System on a programmable chip (SOPC); Field Programmable Gate Array (FPGA)Philadelphia: Elsevier Inc.Information Sciences 181(20), pp.4582–4596This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely togeth
2 100/1 電機系 翁慶昌 教授 期刊論文 發佈 Hardware/software co-design for particle swarm optimization algorithm , [100-1] :Hardware/software co-design for particle swarm optimization algorithm期刊論文Hardware/software co-design for particle swarm optimization algorithmLi, Shih-An; Hsu, Chen-Chien; Wong, Ching-Chang; Yu, Chia-Jun淡江大學電機工程學系HW/SW co-design; Particle swarm optimization (PSO); System on a programmable chip (SOPC); Field Programmable Gate Array (FPGA)Philadelphia: Elsevier Inc.Information Sciences 181(20), pp.4582–4596This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely togeth
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