關鍵字查詢 | 類別:期刊論文 | | 關鍵字:Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

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序號 學年期 教師動態
1 97/2 電機系 楊維斌 副教授 期刊論文 發佈 Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique , [97-2] :Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique期刊論文Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven TechniqueLo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing淡江大學電機工程學系Piscataway: Institute of Electrical and Electronics EngineersIEEE Transactions on Circuits and Systems II: Express Briefs 56(5), pp.339-343This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measur
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