關鍵字查詢 | 類別:期刊論文 | | 關鍵字:Design of an Adjustable-way Cache for Energy Reduction

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序號 學年期 教師動態
1 93/2 電機系 江正雄 教授 期刊論文 發佈 Design of an Adjustable-way Cache for Energy Reduction , [93-2] :Design of an Adjustable-way Cache for Energy Reduction期刊論文Design of an Adjustable-way Cache for Energy ReductionChen, Hsin-chuan; Chiang, Jen-shiun淡江大學電機工程學系Associativity;Adjustable-way;Average energy dissipation;Multiprocessor systemsTaipei : Chinese Institute of Chemical EngineersJournal of the Chinese Institute of Engineers=中國工程學刊 28(4), pp. 691- 700Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an
2 93/2 電機系 陳信全 副教授 期刊論文 發佈 Design of an Adjustable-way Cache for Energy Reduction , [93-2] :Design of an Adjustable-way Cache for Energy Reduction期刊論文Design of an Adjustable-way Cache for Energy ReductionChen, Hsin-chuan; Chiang, Jen-shiun淡江大學電機工程學系Associativity;Adjustable-way;Average energy dissipation;Multiprocessor systemsTaipei : Chinese Institute of Chemical EngineersJournal of the Chinese Institute of Engineers=中國工程學刊 28(4), pp. 691- 700Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an
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