關鍵字查詢 | 類別:期刊論文 | | 關鍵字:An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

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序號 學年期 教師動態
1 99/2 電機系 吳柏翰 助理教授 期刊論文 發佈 An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction , [99-2] :An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction期刊論文An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power ReductionRau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han淡江大學電機工程學系Clock Gating;Scan Test;Low Power Scan Test;Full-Scan Testing;Design for Testability;Yield Loss新北市:淡江大學Tamkang Journal of Science and Engineering=淡江理工學刊 14(1), pp.39-48Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can redu
2 99/2 電機系 饒建奇 副教授 期刊論文 發佈 An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction , [99-2] :An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction期刊論文An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power ReductionRau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han淡江大學電機工程學系Clock Gating;Scan Test;Low Power Scan Test;Full-Scan Testing;Design for Testability;Yield Loss新北市:淡江大學Tamkang Journal of Science and Engineering=淡江理工學刊 14(1), pp.39-48Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can redu
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