1 |
108/1 |
資工系 趙榮耀 教授於
期刊論文
發佈
Establishing a survival probability prediction model for different lung cancer therapies
,
[108-1]
著者:Hsiu-An Lee; Hsiao-Hsien Rau; Louis R. Chao; Chien-Yeh Hsu
|
2 |
105/1 |
物理系 李啟正 助理教授於
期刊論文
發佈
Fermi arc electronic structure and Chern numbers in the type-II Weyl semimetal candidate MoxW1-xTe2
,
[105-1]
著者:Ilya Belopolski, Su-Yang Xu, Yukiaki Ishida, Xingchen Pan, Peng Yu, Daniel S. Sanchez, Hao Zheng, Madhab Neupane, Nasser Alidoust, Guoqing Chang, Tay-Rong Chang, Yun Wu, Guang Bian, Shin-Ming Huang, Chi-Cheng Lee, Daixiang Mou, Lunan Huang, You Song, Baigeng Wang, Guanghou Wang, Yao-Wen Yeh, Nan Yao, Julien E. Rault, Patrick Le Fèvre, François Bertran, Horng-Tay Jeng, Takeshi Kondo, Adam Kaminski, Hsin Lin, Zheng Liu, Fengqi Song, Shik Shin, and M. Zahid Hasan
|
3 |
108/2 |
產經系 李順發 副教授於
期刊論文
發佈
Non-separable Utilities and Aggregate Instability
,
[108-2]
著者:Been-Lon Chen; Shun-Fa Lee; Xavier Raurich
|
4 |
99/1 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
,
[99-1]
著者:Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun
|
5 |
96/2 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
,
[96-2]
著者:Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu
|
6 |
96/2 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
,
[96-2]
著者:Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing
|
7 |
99/2 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
Power-aware compression scheme for multiple scan-chain
,
[99-2]
著者:Rau, Jiann-Chyi; Wu, Po-Han
|
8 |
99/1 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
,
[99-1]
著者:Rau, Jiann-Chyi; Wu, Po-Han
|
9 |
99/2 |
電機系 吳柏翰 助理教授於
期刊論文
發佈
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
,
[99-2]
著者:Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han
|
10 |
102/1 |
物理系 張經霖 教授於
期刊論文
發佈
Disorder-induced Room Temperature Ferromagnetism in Glassy Chromites
,
[102-1]
著者:Moyses Araujo; Sandeep Nagar; Muhammad Ramzan; R. Shukla; O. D. Jayakumar; A. K. Tyagi; Liu, Yi-Sheng; Chen, Jeng-Lung; Per-Anders Glans; Chang, Chinglin 張經霖; Andreas Blomqvist; Raquel Lizárraga; Erik Holmström; Lyubov Belova; Guo, Jinghua; Rajeev Ahuja; K. V. Rao
|
11 |
102/2 |
師培中心 林怡君 助理教授於
期刊論文
發佈
Too Smart to Fail: Perceptions of Asian American Students' Experiences in a Collegiate Honors Program
,
[102-2]
著者:Malik S. Henfield; Hongryun Woo; Lin, Yi-Chun; Meredith A. Rausch
|
12 |
100/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
Test Slice Difference Technique for Low-Transition Test Data Compression
,
[100-2]
著者:Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin
|
13 |
101/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
,
[101-1]
著者:Shih, Chi-Jih; Hsu, Chih-Yao; Kuo, Chun-Yi; Li, James; Rau, Jiann-Chyi; Krishnendu Chakrabarty
|
14 |
99/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
Power-aware compression scheme for multiple scan-chain
,
[99-2]
著者:Rau, Jiann-Chyi; Wu, Po-Han
|
15 |
99/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
,
[99-1]
著者:Rau, Jiann-Chyi; Wu, Po-Han
|
16 |
99/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
,
[99-2]
著者:Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han
|
17 |
97/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
The Efficient TAM Design for Core-Based SOCs Testing
,
[97-1]
著者:Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu
|
18 |
96/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
,
[96-2]
著者:Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing
|
19 |
92/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
以Layout為基礎的高效率多重掃描鍊最佳化
,
[92-2]
著者:饒建奇; Rau, Jiann-chyi
|
20 |
89/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
A timing driven pseudo exhaustive testing for VLSI circuits
,
[89-1]
著者:Chang, Shih-chieh; 饒建奇; Rau, Jiann-chyi
|
21 |
89/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
,
[89-1]
著者:Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L.
|
22 |
92/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
Built-In Reseeding With Modifying Technique For Bist
,
[92-2]
著者:Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu
|
23 |
92/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
,
[92-2]
著者:Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi
|
24 |
92/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
The optimal testrail architecture for core-based soc testing
,
[92-2]
著者:Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung
|
25 |
97/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
,
[97-1]
著者:Rau, Jiann-chyi; Wu, Po-han; Liu, Chia-jung; Lin, Yi-chen
|
26 |
96/2 |
電機系 饒建奇 副教授於
期刊論文
發佈
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
,
[96-2]
著者:Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu
|
27 |
99/1 |
電機系 饒建奇 副教授於
期刊論文
發佈
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
,
[99-1]
著者:Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun
|