A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
學年 98
學期 2
出版（發表）日期 2010-03-01
作品名稱 A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
作品名稱（其他語言）
著者 Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng
單位 淡江大學電機工程學系
出版者 Tokyo: Denshi Jouhou Tsuushin Gakkai
著錄名稱、卷期、頁數 IEICE Transactions on Electronics E93-C(3), pp.309-316
摘要 A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 μm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 μW at 304 MHz.
關鍵字 fractional-N; clock generator; pseudo fractional-N controller; duty cycle
語言 en
ISSN 0916-8524; 1745-1353
期刊性質 國外
收錄於 SCI EI
產學合作
通訊作者 Yang, Wei-Bin
審稿制度 是
國別 JPN
公開徵稿
出版型式 紙本
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