教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
學年85
學期1
發表日期1996/09/23
作品名稱New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
作品名稱(其他語言)
著者Chiang, Jen-shiun; Huang, Hsiang-chou
作品所屬單位淡江大學電機工程學系
出版者N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
會議名稱ASIC Conference and Exhibit, 1996. Ninth Annual IEEE International
會議地點Rochester, NY, USA
摘要The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PLA) to replace multipliers, (2) overlapped row-column operations and pipeline structure to reduce the total computation time, and (3) highly modular and regular structure for the efficient VLSI implementation. The architecture is implemented to a 8×8 2-D DCT. The circuit is designed by UMC's 0.8 μm spdm CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplication and accumulations per second
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間19960923~19960927
通訊作者
國別
公開徵稿Y
出版型式紙本
出處ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International, pp.219-222
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