期刊論文
| 學年 | 53 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 1965-02-01 |
| 作品名稱 | A graphical interpretation of realization of symmetric Boolean functions with threshold logic elements |
| 作品名稱（其他語言） | |
| 著者 | 盛慶琜; Sheng, Ching-lai |
| 單位 | 淡江大學經營決策學系暨管理科學研究所 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 著錄名稱、卷期、頁數 | IEEE transactions on electronic computers EC-14, pp.8-18 |
| 摘要 | A graphical interpretation of the realization of symmetric Boolean functions with threshold logic elements is presented, from which a systematic synthesis method is developed. Theoretically, symmetric functions of any number of variables can be realized. Examples are given to show that, practically, there is no difficulty at all in realizing symmetric Boolean functions of as many as thirty or forty variables. Some theorems related to graphical interpretation and realization are presented, and the lower and upper bounds of the number of threshold logic elements required for the realization of symmetric functions are also derived from the graphical point of view. |
| 關鍵字 | Boolean functions;Indexing;Logic;Information retrieval;Libraries;Testing;Network synthesi |
| 語言 | en_US |
| ISSN | 0367-7508 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/4440 ) |