期刊論文
| 學年 | 86 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 1997-10-01 |
| 作品名稱 | Novel architecture for two-dimensional high throughput rate real-time discrete cosine transform and the VLSI design |
| 作品名稱（其他語言） | |
| 著者 | 江正雄; Chiang, Jen-shiun; Huang, Hsiang-chou |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Abingdon: Taylor & Francis |
| 著錄名稱、卷期、頁數 | International journal of electronics 83(4), pp.519-527 |
| 摘要 | The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and it is important to meet the requirement for high speed. A novel architecture of the VLSI design of a 2D DCT has been developed. This architecture contains the following features: use of the programmable logic array (PLA) to replace multipliers; overlapped row–column operations and pipeline structure to reduce the total computation time; and highly modular and regular structure for the efficient VLSI implementation. This architecture is implemented to a 8 × 8 2D DCT. The circuit is designed by UMC's 0.8 μm SPDM CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplications and accumulations per second. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 0020-7217 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | GBR |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/46401 ) |