期刊論文
| 學年 | 67 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 1978-09-01 |
| 作品名稱 | Effect of Sampling Time Jitter on Array Performance |
| 作品名稱（其他語言） | |
| 著者 | Baker, Charles R.; 趙榮耀; Chow, Louis R. |
| 單位 | 淡江大學資訊工程學系 |
| 出版者 | Piscataway: Institute of Electrical and Electronics Engineers (IEEE) |
| 著錄名稱、卷期、頁數 | IEEE transaction on Aerospace and Electronic Systems Aes-14(5), pp.780-788 |
| 摘要 | The effect on array SNR of errors in sampling times (jitter) isan analyzed for the "Bryn processor." Jitter is modeled as a discrete-paramter er random process, and expressions for array SNR are determined as a function of signal and noise spectra and jitter characteristics. For a plane wave signal, it is found that jitter in the data used to design the processor has no effect on output SNR if the noise is independent between channels. However, jitter in the input (evaluation) n) data can cause a substantial loss in peak array SNR and in the array's frequency selectivity. These losses can be expected to increase as the high-frequency content of the data increases. The Bryn processor also loses its interpretation as a likelihood ratio processor in the presence of jitter. The effect of jitter can be reduced in many cases by increasing the sampling rate. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 0018-9251 |
| 期刊性質 | 國外 |
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| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | USA |
| 公開徵稿 | |
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| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/45360 ) |